Mecrisp

Welcome to the Mecrisp family of native code optimising Forth compilers for MSP430, ARM, RISC-V, MIPS, and stack machines on FPGAs.

Get release packages of everything here.

Mecrisp for MSP430

Mecrisp first ran on the classic 16 bit MSP430 microcontrollers, and still does! On this architecture, the Mecrisp Forth core capable of constant folding needs at least 11 kb of flash and 512 bytes of RAM memory, with the MSP430G2553 being the smallest supported target.

The name Mecrisp derives from French "écris" - I write, you write - and the letters MSP, as in MSP430. Think of it as "you write on the MSP430", as Mecrisp compiles directly into flash memory.

Mecrisp-Across for MSP430

Mecrisp-Across is an experimental cross compiler generating binaries for MSP430 microcontrollers as tiny as the MSP430F2012 and smaller. As a tethered Forth, it gives the illusion of interactively developing Forth code with hardware access to the real target by running the Forth environment on a suitably capable host microcontroller and transparently relaying all peripheral IO access through JTAG/SBW into the real target. As Mecrisp-Across itself has plenty of memory available in the host system, it performs global optimisation of the whole user Forth program, with constant folding, register allocation of both data and return stacks across control structures, automatic inlining and dead code elimination. Out of the box, STM32 F4 Discovery (STM32F407) and Tiva Connected Launchpad (TM4C1294) boards can act as host systems. Loosing interactive hardware insight, one can also choose to compile Forth code into hex files on Linux machines for subsequent flashing .

See the Mecrisp-Across Unofficial Documentation for more!

Mecrisp-Stellaris for ARM

Mecrisp-Stellaris runs on a wide selection of ARM Cortex M0, M3, M4 microcontrollers, also including targets running directly on Linux and FreeBSD.

See the Mecrisp-Stellaris Unofficial Documentation for more!

You can choose between two different compilers: The legacy compiler is capable of constant folding and needs 16 kb flash, whereas the "RA" compiler needs 20 kb flash, and also performs automatic inlining and a register allocation for the data stack. If your chip offers 32 kb flash or more, go with the "RA" one!

The Forth core of Mecrisp-Stellaris in the 2.x.x branch as maintained here is stable and functionally complete.

For shiny new experimental features beyond the limits of the tiniest ARM Cortex microcontrollers, keep an eye on the upcoming experimental 3.x.x branch. In the clausecker/mecrisp-stellaris repository on Codeberg new core features will be implemented by a team of fresh maintainers that embrace the capabilities of current targets.

Mecrisp-Quintus for RISC-V and MIPS

Mecrisp-Quintus runs on 32 bit RISC-V (RV32I, RV32IM, RV32IMC) and MIPS (M4K) targets, also including variants running on Linux. Typical Forth core sizes are between 18 kb and 30 kb depending on the amount of necessary target specific code, processor architecture and the availability of compressed instructions. The Forth cores as-is perform constant folding. Stronger optimisations like automatic inlining and register allocation for both data and return stack are available as loadable "Acrobatics" compiler extension written in Forth.

Mecrisp-Quintus also contains a selection of different RISC-V softcore designs for FPGA boards based on the FemtoRV32 processor family developed together with Bruno Levy.

Mecrisp-Ice for FPGA

Mecrisp-Ice is a 16 bit Forth running on a stack machine specifically developed for FPGAs, originally based on Swapforth and the J1a processor by James Bowman. Mecrisp-Ice requires initialised single-cycle dualport RAM blocks to run and is developed with excellent realtime capabilities and deterministic interrupt timing in mind. Due to instruction set design, the maximum (and recommended) amount of addressable executable memory is 16 kb, with an usable minimum of 8 kb.

The 16 bit implementation is stable and rock solid, whereas the 32 bit and 64 bit implementations with support for larger executable memories should be considered experimental.

Great things elsewhere

• Repositories and demoscene entries of the same author.
• Bruno Levy created an introduction to RISC-V processor design on FPGAs.
• Zeptoforth, a different Forth implementation for ARM Cortex with strong multitasking and multicore support. Comes with a port for the Raspberry Pi Pico featuring a native USB terminal.
• Peter Schmid, who wished to use Mecrisp-Stellaris together with C libraries, solved the integration of Forth into C in his Mecrisp-Cube project for STM32 microcontrollers.

Get in touch

Have a look into the forum for help and discussion first.

Join us in our IRC channels on Hackint: #mecrisp is mostly for Linux/FreeBSD ports and compiler design ideas, moderated by Robert Clausecker. #forth-hardware-projects is your choice if your project runs on microcontrollers and requires soldering, moderated by Terry Porter. You can also join #mecrisp on Libera.

On Matrix, there is no special Mecrisp room yet, but you can join #forth:matrix.org for general questions regarding Forth.